(continued) at28bv64 64k (8k x 8) battery-voltage ? cmos e 2 prom features 2.7v to 3.6v supply full read and write operation low power dissipation 8 ma active current 50 m a cmos standby current read access time - 300 ns byte write - 3 ms direct microprocessor control data polling ready/ busy open drain output high reliability cmos technology endurance: 100,000 cycles data retention: 10 years jedec approved byte-wide pinout commercial and industrial temperature ranges description the at28bv64 is a low-voltage, low-power electrically erasable and programmable read only memory specifically designed for battery powered applications. its 64k of memory is organized 8,192 words by 8 bits. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 200 ns with power dissipation less than 30 mw. when the device is deselected the standby current is less than 50 m a. the at28bv64 is accessed like a static ram for the read or write cycles without the need for external components. during a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. fol- plcc top view tsop top view pdip, soic top view pin name function a0 - a12 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs rdy/ busy ready/ busy output nc no connect dc dont connect pin configurations 0493a at28bv64 2-127
block diagram temperature under bias................. -55c to +125c storage temperature...................... -65c to +150c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* lowing the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. the device includes two methods for detecting the end of a write cycle, level detection of rdy/ busy and data polling of i/o 7 . once the end of a write cycle has been detected, a new access for a read or write can begin. atmels 28bv64 has additional features to ensure high quality and manufacturability. the device utilizes error cor- rection internally for extended endurance and for im- proved data retention characteristics. an extra 32-bytes of e 2 prom are available for device identification or tracking. description (continued) 2-128 at28bv64
device operation read: the at28bv64 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in a high im- pedance state whenever ce or oe is high. this dual line control gives designers increased flexibility in preventing bus contention. byte write: writing data into the at28bv64 is similar to writing into a static ram. a low pulse on the we or ce input with oe high and ce or we low (respectively) initi- ates a byte write. the address location is latched on the falling edge of we (or ce); the new data is latched on the rising edge. internally, the device performs a self-clear be- fore write. once a byte write has been started, it will auto- matically time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effectively be a polling operation. ready/ busy: pin 1 is an open drain ready/ busy output that can be used to detect the end of a write cycle. rdy/ busy is actively pulled low during the write cycle and is released at the completion of the write. the open drain connection allows for or-tying of several devices to the same rdy/ busy line. data polling: the at28bv64 provides data polling to signal the completion of a write cycle. during a write cycle, an attempted read of the data being written results in the complement of that data for i/o 7 (the other outputs are indeterminate). when the write cycle is fin- ished, true data appears on all outputs. write protection: inadvertent writes to the device are protected against in the following ways. (a) v cc sense if v cc is below 1.8v (typical) the write function is inhibited. (b) v cc power on delay once v cc has reached 2.0v the device will automatically time out 10 ms (typical) before allowing a byte write. (c) write inhibit holding any one of oe low, ce high or we high inhibits byte write cycles. at28bv64 2-129
symbol parameter condition min max units i li input load current v in = 0v to v cc + 1.0v 5 m a i lo output leakage current v i/o = 0v to v cc 5 m a i sb v cc standby current cmos ce = v cc - 0.3v to v cc + 1.0v 50 m a i cc v cc active current ac f = 5 mhz; i out = 0 ma; ce = v il 8ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1 ma 0.3 v i ol = 2 ma for rdy/ busy 0.3 v v oh output high voltage i oh = -100 m a 2.0 v dc characteristics at28bv64-30 operating temperature (case) com. 0c - 70c ind. -40c - 85c v cc power supply 2.7v to 3.6v dc and ac operating range mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. operating modes 2-130 at28bv64
at28bv64-30 symbol parameter min max units t acc address to output delay 300 ns t ce (1) ce to output delay 300 ns t oe (2) oe to output delay 0 150 ns t df (3, 4) ce or oe high to output float 0 60 ns t oh output hold from oe, ce or address, whichever occurred first 0ns ac read characteristics ac read waveforms (1, 2, 3, 4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. t r , t f < 20 ns input test waveforms and measurement level output test load typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v pin capacitance (f = 1 mhz, t = 25c) (1) note: 1. this parameter is characterized and is not 100% tested. at28bv64 2-131
symbol parameter min max units t as , t oes address, oe set-up time 10 ns t ah address hold time 100 ns t wp write pulse width ( we or ce) 150 1000 ns t ds data set-up time 100 ns t dh , t oeh data, oe hold time 10 ns t db time to device busy 50 ns t wc write cycle time 3 ms ac write characteristics ac write waveforms we controlled ce controlled 2-132 at28bv64
symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns data polling characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. data polling waveforms at28bv64 2-133
ordering information (1) t acc (ns) i cc (ma) operating voltage ordering code package operation range active standby 300 8 0.05 2.7v to 3.6v at28bv64-30jc 32j commercial AT28BV64-30PC 28p6 (0 c to 70 c) at28bv64-30sc 28s at28bv64-30tc 28t 8 0.05 2.7v to 3.6v at28bv64-30ji 32j industrial at28bv64-30pi 28p6 (-40 c to 85 c) at28bv64-30si 28s at28bv64-30ti 28t note: 1. see valid part number table below. package type 32j 32 lead, plastic j-leaded chip carrier (plcc) 28p6 28 lead, 0.600" wide, plastic dual inline package (pdip) 28s 28 lead, 0.300" wide, plastic gull wing, small outline (soic) 28t 28 lead, plastic thin small outline package (tsop) the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28bv64 30 jc, ji, pc, pi, sc, si, tc, ti valid part numbers 2-134 at28bv64
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